DSL's - Revision history

imported>ChunhuaLiao at 00:07, May 23, 2014

2014-05-23T00:07:10Z

← Older revision		Revision as of 00:07, May 23, 2014
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	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''D-TEC		\|''D-TEC
	\| ~~Heterogeneous OpenMP~~		\| X-GEN for heterogenous computing
	\| http://rosecompiler.org/		\| http://rosecompiler.org/
	\| HPC applications running on NVIDIA GPUs		\| HPC applications running on NVIDIA GPUs

2014-05-16T00:10:28Z

2014-05-16T00:09:38Z

DEGAS entry

2014-05-16T00:08:03Z

DEGAS entry

← Older revision		Revision as of 00:08, May 16, 2014
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	\|HPC Toolkit		\|HPC Toolkit
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''DSL 8		\|''DEGAS"
	\|		\|Asp
			\|http://sejits.org
			\|Infrastructure for building embedded Python DSLs
			\|
			\|Python syntax
			\|custom IR based on Python's AST
			\|Key optimizations performed: loop transformations, vectorization, template-based code generation, caching
			\|LLVM (in progress), C, C++, Scala, CUDA, OpenCL
			\|x86, Nvidia GPUs, cloud, MPI
			\|Numerous DSLs including structured grids, recursive communication-avoiding matmult, machine learning algorithms, communication-avoiding solvers
			\|Structured grid DSL achieves 90%+ peak for many kernels on multiple platforms
			\|In-progress. tech report on multi-tiered strategy.
			\|- style="vertical-align:top;"
			\|''DSL 9
	\|		\|
	\|		\|

2014-05-12T22:18:12Z

← Older revision		Revision as of 22:18, May 12, 2014
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	\| - Basic kernel generation - Directives parsing - Runtime tested on Nividia GPUs, Intel CPUs, and Intel XeonPhi		\| - Basic kernel generation - Directives parsing - Runtime tested on Nividia GPUs, Intel CPUs, and Intel XeonPhi
	\| Reaches ~50 Gflops on Tesla M2070 on matrix multiply. (M2070: ~1Tflops peaks, ~200 to ~400 Gflops effective on linear algebra ; all floating point).		\| Reaches ~50 Gflops on Tesla M2070 on matrix multiply. (M2070: ~1Tflops peaks, ~200 to ~400 Gflops effective on linear algebra ; all floating point).
	\| A profiling interface collects OpenCL profiling information in DB.		\| A profiling interface collects OpenCL profiling information in a database.
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''D-TEC		\|''D-TEC

2014-05-12T22:17:48Z

← Older revision		Revision as of 22:17, May 12, 2014
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	\| implementation in progress.		\| implementation in progress.
	\| 1.7x performance improvement compared to OpenMP implementation for 2D 2nd order stencil computation.		\| 1.7x performance improvement compared to OpenMP implementation for 2D 2nd order stencil computation.
	\|		\| PAPI is used for for performance profiling. libnuma and internal debugging scheme are used to verify memory distribution among NUMA nodes.
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''D-TEC		\|''D-TEC

2014-05-12T18:16:50Z

2014-05-12T18:11:40Z

← Older revision		Revision as of 18:11, May 12, 2014
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	\| - Basic kernel generation - Directives parsing - Runtime tested on Nividia GPUs, Intel CPUs, and Intel XeonPhi		\| - Basic kernel generation - Directives parsing - Runtime tested on Nividia GPUs, Intel CPUs, and Intel XeonPhi
	\| Reaches ~50 Gflops on Tesla M2070 on matrix multiply. (M2070: ~1Tflops peaks, ~200 to ~400 Gflops effective on linear algebra ; all floating point).		\| Reaches ~50 Gflops on Tesla M2070 on matrix multiply. (M2070: ~1Tflops peaks, ~200 to ~400 Gflops effective on linear algebra ; all floating point).
	\|		\| A profiling interface collects OpenCL profiling information in DB.
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''D-TEC		\|''D-TEC

2014-05-12T18:11:38Z

← Older revision		Revision as of 18:11, May 12, 2014
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	\|		\|
	\|		\|
			\|- style="vertical-align:top;"
			\|''D-TEC
			\| Simit
			\|
			\| Computations on domains expressible as a graph
			\| Internal physics simulations, Lulesh, MiniFE, phdMesh, MiniGhost
			\| Uses C++
			\| Custom IR
			\| Fusion, Blocking, Vectorization, Parallelization, Distribution, Graph Index Sets
			\| LLVM
			\| X86 multicores, GPU and later distributed systems
			\| Design and implementation in progress
			\|
			\| Has a visual backend.
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''TG X-Stack''		\|''TG X-Stack''
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	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''DSL 8		\|''DSL 8
	\|		\|
	\|		\|
	\|		\|

2014-05-12T18:01:33Z

← Older revision		Revision as of 18:01, May 12, 2014
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	\|Implementation released (4/28/2014)		\|Implementation released (4/28/2014)
	\|Being evaluated for use		\|Being evaluated for use
	\|		\|Work in progress
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|''D-TEC		\|''D-TEC
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	\| Implementation released with ROSE (4/29/2014)		\| Implementation released with ROSE (4/29/2014)
	\| Matches or outperforms caparable compilers targeting GPUs.		\| Matches or outperforms caparable compilers targeting GPUs.
	\|		\| Generate event traces for gpuplot to identify serial bottleneck
	\|- style="vertical-align:top;"		\|- style="vertical-align:top;"
	\|'' D-TEC		\|'' D-TEC