imported>ChunhuaLiao: /* D-TEC: DSL Technology for Exascale Computing */

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D-TEC: DSL Technology for Exascale Computing

← Older revision		Revision as of 20:49, June 18, 2015
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	# Kevin Alan Stock. Vectorization and Register Reuse in High Performance Computing. PhD thesis, The Ohio State University, 2014.		# Kevin Alan Stock. Vectorization and Register Reuse in High Performance Computing. PhD thesis, The Ohio State University, 2014.
	# Tom Henretty, Richard Veras, Franz Franchetti, Louis-Noel Pouchet, J. Ramanujam, and P. Sadayappan. A stencil compiler for short-vector simd architectures. In Proceedings of the 27th International ACM Conference on International Conference on Supercomputing, ICS '13, pages 13{24, New York, NY, USA, 2013. ACM.		# Tom Henretty, Richard Veras, Franz Franchetti, Louis-Noel Pouchet, J. Ramanujam, and P. Sadayappan. A stencil compiler for short-vector simd architectures. In Proceedings of the 27th International ACM Conference on International Conference on Supercomputing, ICS '13, pages 13{24, New York, NY, USA, 2013. ACM.
	# Justin Holewinski, Louis-Noel Pouchet, and P. Sadayappan. High-performance code generation		# Justin Holewinski, Louis-Noel Pouchet, and P. Sadayappan. High-performance code generation for stencil computations on gpu architectures. In Proceedings of the 26th ACM International Conference on Supercomputing, ICS '12, pages 311{320, New York, NY, USA, 2012. ACM.
	for stencil computations on gpu architectures. In Proceedings of the 26th ACM International
	Conference on Supercomputing, ICS '12, pages 311{320, New York, NY, USA, 2012. ACM.
	# Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, and Jason Cong. Polyhedral-based data reuse optimization for configurable computing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, pages 29{38, New York, NY, USA, 2013. ACM.		# Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, and Jason Cong. Polyhedral-based data reuse optimization for configurable computing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, pages 29{38, New York, NY, USA, 2013. ACM.
	# S. Rajbhandari, A. Nikam, Pai-Wei Lai, K. Stock, S. Krishnamoorthy, and P. Sadayappan. Cast: Contraction algorithm for symmetric tensors. In Parallel Processing (ICPP), 2014 43rd International Conference on, pages 261{272, Sept 2014.		# S. Rajbhandari, A. Nikam, Pai-Wei Lai, K. Stock, S. Krishnamoorthy, and P. Sadayappan. Cast: Contraction algorithm for symmetric tensors. In Parallel Processing (ICPP), 2014 43rd International Conference on, pages 261{272, Sept 2014.

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imported>ChunhuaLiao: Created page with "==D-TEC: DSL Technology for Exascale Computing== List * Markus Schordan, Pei-Hung Lin, Dan Quinlan, and Louis-Nol Pouchet. Veri�cation of polyhedral optimizations with con..."

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==D-TEC: DSL Technology for Exascale Computing==
List
* Markus Schordan, Pei-Hung Lin, Dan Quinlan, and Louis-Nol Pouchet. Veri�cation of polyhedral
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* Chunhua Liao, Daniel J. Quinlan, Thomas Panas, and Bronis R. de Supinski. A rose-based
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* Chunhua Liao, Yonghong Yan, Bronis R de Supinski, Daniel J Quinlan, and Barbara Chapman.
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* Dan Quinlan and Chunhua Liao. The ROSE source-to-source compiler infrastructure. In Cetus
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* Yonghong Yan, Pei-Hung Lin, Chunhua Liao, Bronis R. de Supinski, and Daniel J. Quinlan.
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Pei-Hung Lin, Chunhua Liao, Daniel J. Quinlan, and Stephen Guzik. Experiences of using
the openmp accelerator model to port doe stencil applications, 2014. Poster presented at the
Workshop on accelerator programming using directives, Nov. 17, 2014, New Orleans, LA.
* Markus Schordan, Pei-Hung Lin, Dan Quinlan, and Louis-Nol Pouchet. Veri�cation of parallel
polyhedral transformations with arbitrary constant loop bounds, 2015. In review process of
EuroPar2015.
* Jonathan Ragan-Kelley. Decoupling Algorithms from the Organization of Computation for High
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mance Computing, Networking, Storage and Analysis, SC '14, pages 311{322, Piscataway, NJ,
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[27] David Grove, Josh Milthorpe, and Olivier Tardieu. Supporting array programming in X10. In
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[28] Wei Zhang, Olivier Tardieu, David Grove, Benjamin Herta, Tomio Kamada, Vijay Saraswat,
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to the 2013 HPC Class II Challenge, October 2013.
[30] Craig Rasmussen, Matthew Sottile, Daniel Nagle, and Soren Rasmussen. Locally-oriented
programming: A simple programming model for stencil-based computations on multi-level distributed
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[31] Thomas Steel Henretty. Performance Optimization of Stencil Computations on Modern SIMD
Architectures. PhD thesis, The Ohio State University, 2014.
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array access patterns. PhD thesis, The Ohio State University, 2014.
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[35] Tom Henretty, Richard Veras, Franz Franchetti, Louis-Noel Pouchet, J. Ramanujam, and
P. Sadayappan. A stencil compiler for short-vector simd architectures. In Proceedings of the
27th International ACM Conference on International Conference on Supercomputing, ICS '13,
pages 13{24, New York, NY, USA, 2013. ACM.
[36] Justin Holewinski, Louis-Noel Pouchet, and P. Sadayappan. High-performance code generation
for stencil computations on gpu architectures. In Proceedings of the 26th ACM International
Conference on Supercomputing, ICS '12, pages 311{320, New York, NY, USA, 2012. ACM.
[37] Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, and Jason Cong. Polyhedral-based data
reuse optimization for con�gurable computing. In Proceedings of the ACM/SIGDA International
Symposium on Field Programmable Gate Arrays, FPGA '13, pages 29{38, New York, NY, USA,
2013. ACM.
[38] S. Rajbhandari, A. Nikam, Pai-Wei Lai, K. Stock, S. Krishnamoorthy, and P. Sadayappan.
Cast: Contraction algorithm for symmetric tensors. In Parallel Processing (ICPP), 2014 43rd
International Conference on, pages 261{272, Sept 2014.
[39] Samyam Rajbhandari, Akshay Nikam, Pai-Wei Lai, Kevin Stock, Sriram Krishnamoorthy,
and P. Sadayappan. A communication-optimal framework for contracting distributed tensors.
In Proceedings of the International Conference for High Performance Computing, Networking,
Storage and Analysis, SC '14, pages 375{386, Piscataway, NJ, USA, 2014. IEEE Press.
[40] Mahesh Ravishankar, John Eisenlohr, Louis-Noel Pouchet, J. Ramanujam, Atanas Rountev,
and P. Sadayappan. Code generation for parallel execution of a class of irregular loops on distributed
memory systems. In Proceedings of the International Conference on High Performance
Computing, Networking, Storage and Analysis, SC '12, pages 72:1{72:11, Los Alamitos, CA,
USA, 2012. IEEE Computer Society Press.
[41] Mahesh Ravishankar, John Eisenlohr, Louis-Noel Pouchet, J. Ramanujam, Atanas Rountev,
and P. Sadayappan. Automatic parallelization of a class of irregular loops for distributed
memory systems. ACM Transactions on Parallel Computing, 1(1):7:1{7:37, September 2014.
[42] Mahesh Ravishankar, Roshan Dathathri, Venmugil Elango, Louis-Noel Pouchet, J Ramanujam,
Atanas Rountev, and P Sadayappan. Distributed memory code generation for mixed
irregular/regular computations. In Proceedings of the 20th ACM SIGPLAN Symposium on
Principles and Practice of Parallel Programming, pages 65{75. ACM, 2015.
[43] Kevin Stock, Martin Kong, Tobias Grosser, Louis-Noel Pouchet, Fabrice Rastello, J. Ramanujam,
and P. Sadayappan. A framework for enhancing data reuse via associative reordering.
In Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and
Implementation, PLDI '14, pages 65{76, New York, NY, USA, 2014. ACM.
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On characterizing the data movement complexity of computational dags for parallel execution.
In Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures,
SPAA '14, pages 296{306, New York, NY, USA, 2014. ACM.
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Atanas Rountev, Louis-Noel Pouchet, and P. Sadayappan. Beyond reuse distance analysis:
Dynamic analysis for characterization of data locality potential. ACM Trans. Archit. Code
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[46] Martin Kong, Richard Veras, Kevin Stock, Franz Franchetti, Louis-Noel Pouchet, and P. Sadayappan.
When polyhedral transformations meet simd code generation. In Proceedings of
the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation,
PLDI '13, pages 127{138, New York, NY, USA, 2013. ACM.
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19th International Workshop on High-level Parallel Programming Models and Supportive Envi-
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and ast-based transformations. In IEEE Conference on High Performance Computing,
Networking, Storage and Analysis (SC'14). IEEE, 2014.
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programs. In 5th International Workshop on Polyhedral Compilation Techniques (IMPACT
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and AST-based Transformations. In 17th Workshop on Compilers for Parallel Programming,
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imported>ChunhuaLiao: /* D-­TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-­TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-­TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-­TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: Created page with "==D-­TEC: DSL Technology for Exascale Computing== List * Markus Schordan, Pei-Hung Lin, Dan Quinlan, and Louis-Nol Pouchet. Veri�cation of polyhedral optimizations with con..."

imported>ChunhuaLiao: /* D-TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: /* D-TEC: DSL Technology for Exascale Computing */

imported>ChunhuaLiao: Created page with "==D-TEC: DSL Technology for Exascale Computing== List * Markus Schordan, Pei-Hung Lin, Dan Quinlan, and Louis-Nol Pouchet. Veri�cation of polyhedral optimizations with con..."