Traleika Glacier: Difference between revisions
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| image = [[File:Your-team-logo.png|180px]] | | image = [[File:Your-team-logo.png|180px]] | ||
| imagecaption = | | imagecaption = | ||
| team-members = | | team-members = [http://www.intel.com/ Intel], [https://www.reservoir.com/ Reservoir Labs], [http://www.etinternational.com/ ETI], [http://www.udel.edu/ UDEL], [http://www.ucsd.edu/ UC San Diego], [http://www.rice.edu/ Rice U.], [http://cs.illinois.edu/ UIUC], [http://www.pnnl.gov/ PNNL], [http://www.sandia.gov/ SNL] | ||
| pi = | | pi = Shekhar Borkar (Intel) | ||
| co-pi = | | co-pi = Wilf Pinfold (Intel), Richard Lethin (Reservoir Labs), Rishi Khan (ETI), Guang Gao (UDEL), Laura Carrington (UC San Diego), Vivek Sarkar (Rice U.), David Padua (UIUC), Josep Torrellas (UIUC), John Feo (PNNL), Jackie Chen (SNL) | ||
| website = | | website = [https://sites.google.com/site/traleikaglacierxstack/ https://sites.google.com/site/traleikaglacierxstack] | ||
}} | }} | ||
'' | |||
'''Traleika Glacier''' | |||
== Team Members == | == Team Members == | ||
* [http://www.intel.com/ Intel:] Hardware guidance, HW/SW co-design, resiliency, technical management | |||
* [https://www.reservoir.com/ Reservoir Labs:] Programming system, R-Stream, tools, optimization | |||
* [http://www.etinternational.com/ ET International (ETI):] Simulators, execution model and runtime support | |||
* [http://www.udel.edu/ University of Delaware (UDEL):] Execution model research | |||
* [http://www.ucsd.edu/ University of California, San Diego (UC San Diego):] Applications | |||
* [http://www.rice.edu/ Rice University:] Programming system, runtime system | |||
* [http://cs.illinois.edu/ University of Illinois at Urbana-Champaign (UIUC):] Programming system, Hierarchical Tiles Arrays (HTA), architecture, system architecture evaluation | |||
* [http://www.pnnl.gov/ Pacific Northwest National Laboratory (PNNL):] Kernels and proxy apps for evaluation | |||
* [http://www.sandia.gov/ Sandia National Lab (SNL):] Co-design lead, combustion proxy app | |||
== Goals and Objectives == | |||
'''Goal:''' | |||
* Research and mature software technologies addressing major Exascale challenges and get ready to intercept by 2018-2020 | |||
'''Objectives:''' | |||
== | * '''Energy efficiency:''' SW components interoperate, harmonize, exploit HW features, and optimize the system for energy efficiency | ||
* '''Data locality:''' PGM system & system SW optimize to reduce data movement | |||
* '''Scalability:''' SW components scalable, portable to O(109)—extreme parallelism | |||
* '''Programmability:''' New (Codelet) & legacy (MPI), with gentle slope for productivity | |||
* '''Execution model:''' Objective function based, dynamic, global system optimization | |||
* '''Self-awareness:''' Dynamically respond to changing conditions and demands | |||
* '''Resiliency:''' Asymptotically provide reliability of N-modular redundancy using HW/SW co-design; HW detection, SW correction | |||
== Scope of the Project == | |||
[[File:TG-Scope.png|600px]] | |||
== Roadmap == | == Roadmap == | ||
[[File:TG-Roadmap.png]] | |||
== Architecture == | |||
'''Straw-man System Architecture and Evaluation''' | |||
[[File:TG-Strawman-System.png|600px]] | |||
'''Data-locality and BW Tapering, Why So Important?''' | |||
[[File:TG-Data-Locality.png|600px]] | |||
== Programming and Execution Models == | |||
[[File:TG-Programming-Model.png]] | |||
'''Programming model''' | |||
* Separation of concerns: Domain specification & HW mapping | |||
* Express data locality with hierarchical tiling | |||
* Global, shared, non-coherent address space | |||
* Optimization and auto generation of codelets (HW specific) | |||
'''Execution model''' | |||
* Dataflow inspired, tiny codelets (self contained) | |||
* Dynamic, event-driven scheduling, non-blocking | |||
* Dynamic decision to move computation to data | |||
* Observation based adaption (self-awareness) | |||
* Implemented in the runtime environment | |||
'''Separation of concerns''' | |||
* User application, control, and resource management | |||
=== Programming System Components === | |||
[[File:TG-System-Components.png|600px]] | |||
=== Runtime === | |||
* Different runtimes target different aspects | |||
** IRR: targeted for Intel Straw-man architecture | |||
** SWARM: runtime for a wide range of parallel machines | |||
** DAR3TS: explore codelet PXM using portable C++ | |||
** Habanero-C: interfaces IRR, tie-in to CnC | |||
* All explore related aspects of the codelet Program Exec Model (PXM) | |||
* Goal: Converge towards Open Collaborative Runtime (OCR) | |||
** Enabling technology development for codelet execution | |||
** Model systems, foster novel runtime systems research | |||
* Greater visibility through SW stack -> efficient computing | |||
** Break OS/Runtime information firewall | |||
'''Some Promising Results:''' | |||
[[File:TG-Runtime-Results.png|600px]] | |||
'''Runtime Research Agenda''' | |||
* Locality aware scheduling—heuristics for locality/E-efficiency | |||
** Extensions to standard Habanero-C runtime | |||
* Adaptive boosting and idling of hardware | |||
** Avoid energy expensive unsuccessful steals that perform no work | |||
** Turbo mode for a core executing serial code | |||
** Fine grain resource (including energy) management | |||
* Dynamic data-block movement | |||
** Co-locate codelets and data | |||
** Move codelets to data | |||
* Introspection and dynamic optimization | |||
** Performance counters, sensors provide real time information | |||
** Optimization of the system for user defined objective | |||
** (Go beyond energy proportional computing) | |||
=== Simulators and Tools === | |||
[[File:TG-Simulators-Tools.png|600px]] | |||
'''Simulators—what to expect and not''' | |||
* Evaluation of architecture features for PGM and EXE models | |||
* Relative comparison of performance, energy | |||
* Data movement patterns to memory and interconnect | |||
* Relative evaluation of resource management techniques | |||
[[File:TG-Simulator-Expect-Not.png|400px]] | |||
'''Results Using Simulators''' | |||
[[File:TG-Simulator-Results.png|600px]] | |||
== Applications and HW-SW Codesign == | |||
[[File:TG-App-HW-Co-design.png|600px]] | |||
== | == X-Stack Components == | ||
[[File:TG-XStack-Components.png|600px]] | |||
== | == Metrics == | ||
[[File:TG-Metrics.png|600px]] |
Revision as of 18:02, February 7, 2013
Traleika Glacier | |
---|---|
File:Your-team-logo.png | |
Team Members | Intel, Reservoir Labs, ETI, UDEL, UC San Diego, Rice U., UIUC, PNNL, SNL |
PI | Shekhar Borkar (Intel) |
Co-PIs | Wilf Pinfold (Intel), Richard Lethin (Reservoir Labs), Rishi Khan (ETI), Guang Gao (UDEL), Laura Carrington (UC San Diego), Vivek Sarkar (Rice U.), David Padua (UIUC), Josep Torrellas (UIUC), John Feo (PNNL), Jackie Chen (SNL) |
Website | https://sites.google.com/site/traleikaglacierxstack |
Download | {{{download}}} |
Traleika Glacier
Team Members
- Intel: Hardware guidance, HW/SW co-design, resiliency, technical management
- Reservoir Labs: Programming system, R-Stream, tools, optimization
- ET International (ETI): Simulators, execution model and runtime support
- University of Delaware (UDEL): Execution model research
- University of California, San Diego (UC San Diego): Applications
- Rice University: Programming system, runtime system
- University of Illinois at Urbana-Champaign (UIUC): Programming system, Hierarchical Tiles Arrays (HTA), architecture, system architecture evaluation
- Pacific Northwest National Laboratory (PNNL): Kernels and proxy apps for evaluation
- Sandia National Lab (SNL): Co-design lead, combustion proxy app
Goals and Objectives
Goal:
- Research and mature software technologies addressing major Exascale challenges and get ready to intercept by 2018-2020
Objectives:
- Energy efficiency: SW components interoperate, harmonize, exploit HW features, and optimize the system for energy efficiency
- Data locality: PGM system & system SW optimize to reduce data movement
- Scalability: SW components scalable, portable to O(109)—extreme parallelism
- Programmability: New (Codelet) & legacy (MPI), with gentle slope for productivity
- Execution model: Objective function based, dynamic, global system optimization
- Self-awareness: Dynamically respond to changing conditions and demands
- Resiliency: Asymptotically provide reliability of N-modular redundancy using HW/SW co-design; HW detection, SW correction
Scope of the Project
Roadmap
Architecture
Straw-man System Architecture and Evaluation
Data-locality and BW Tapering, Why So Important?
Programming and Execution Models
Programming model
- Separation of concerns: Domain specification & HW mapping
- Express data locality with hierarchical tiling
- Global, shared, non-coherent address space
- Optimization and auto generation of codelets (HW specific)
Execution model
- Dataflow inspired, tiny codelets (self contained)
- Dynamic, event-driven scheduling, non-blocking
- Dynamic decision to move computation to data
- Observation based adaption (self-awareness)
- Implemented in the runtime environment
Separation of concerns
- User application, control, and resource management
Programming System Components
Runtime
- Different runtimes target different aspects
- IRR: targeted for Intel Straw-man architecture
- SWARM: runtime for a wide range of parallel machines
- DAR3TS: explore codelet PXM using portable C++
- Habanero-C: interfaces IRR, tie-in to CnC
- All explore related aspects of the codelet Program Exec Model (PXM)
- Goal: Converge towards Open Collaborative Runtime (OCR)
- Enabling technology development for codelet execution
- Model systems, foster novel runtime systems research
- Greater visibility through SW stack -> efficient computing
- Break OS/Runtime information firewall
Some Promising Results:
Runtime Research Agenda
- Locality aware scheduling—heuristics for locality/E-efficiency
- Extensions to standard Habanero-C runtime
- Adaptive boosting and idling of hardware
- Avoid energy expensive unsuccessful steals that perform no work
- Turbo mode for a core executing serial code
- Fine grain resource (including energy) management
- Dynamic data-block movement
- Co-locate codelets and data
- Move codelets to data
- Introspection and dynamic optimization
- Performance counters, sensors provide real time information
- Optimization of the system for user defined objective
- (Go beyond energy proportional computing)
Simulators and Tools
Simulators—what to expect and not
- Evaluation of architecture features for PGM and EXE models
- Relative comparison of performance, energy
- Data movement patterns to memory and interconnect
- Relative evaluation of resource management techniques
Results Using Simulators
Applications and HW-SW Codesign
X-Stack Components