DSL's: Difference between revisions
From Modelado Foundation
imported>Dquinlan No edit summary |
imported>Dquinlan (Minor edits for formatting.) |
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
|''Xstack projects involved | |''Xstack projects involved | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Internal representation used | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Key Optimizations performed | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Code generation technology used | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Processors/computing models targeted | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Current status | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
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|(PIPER) | |(PIPER) | ||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
| | |''Summary of the best results | ||
|(EXPRESS) | |(EXPRESS) | ||
|(TG) | |(TG) | ||
Revision as of 15:20, April 29, 2014
Sonia requested that Saman Amarasinghe and Dan Quinlan initiate this page. For comments, please contact them. This page is still in development.
| QUESTIONS | XPRESS | TG X-Stack | DEGAS | D-TEC | DynAX | X-TUNE | GVR | CORVETTE | SLEEC | PIPER |
|---|---|---|---|---|---|---|---|---|---|---|
| PI | Ron Brightwell | Shekhar Borkar | Katherine Yelick | Daniel Quinlan | Guang Gao | Mary Hall | Andrew Chien | Koushik Sen | Milind Kulkarni | Martin Schulz |
| Name of the DSL | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | SLEEC | (PIPER) |
| 'URL: | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Target domain | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Miniapps supported | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Xstack projects involved | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Internal representation used | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Key Optimizations performed | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Code generation technology used | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Processors/computing models targeted | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Current status | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |
| Summary of the best results | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |