DSL's: Difference between revisions
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! style="width: 200;" | QUESTIONS | ! style="width: 200;" | QUESTIONS | ||
! style="width: 200;" | DSL | ! style="width: 200;" | Name of the DSL | ||
! style="width: 200;" | | ! style="width: 200;" | Associated X-Stack Project | ||
! style="width: 200;" | | ! style="width: 200;" | URL | ||
! style="width: 200;" | | ! style="width: 200;" | Target domain | ||
! style="width: 200;" | | ! style="width: 200;" | Miniapps supported | ||
! style="width: 200;" | | ! style="width: 200;" | Front-end technology used | ||
! style="width: 200;" | | ! style="width: 200;" | Internal representation used | ||
! style="width: 200;" | | ! style="width: 200;" | Key Optimizations performed | ||
! style="width: 200;" | | ! style="width: 200;" | Code generation technology used | ||
! style="width: 200;" | | ! style="width: 200;" | Processors/computing models targeted | ||
! style="width: 200;" | Current status | |||
! style="width: 200;" | Summary of the best results | |||
|- style="vertical-align:top;" | |- style="vertical-align:top;" | ||
|Name of the DSL | |Name of the DSL | ||
Revision as of 16:00, April 29, 2014
Sonia requested that Saman Amarasinghe and Dan Quinlan initiate this page. For comments, please contact them. This page is still in development.
| QUESTIONS | Name of the DSL | Associated X-Stack Project | URL | Target domain | Miniapps supported | Front-end technology used | Internal representation used | Key Optimizations performed | Code generation technology used | Processors/computing models targeted | Current status | Summary of the best results |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Name of the DSL | ||||||||||||
| Associated X-Stack Project | ||||||||||||
| URL | ||||||||||||
| Target domain | ||||||||||||
| Miniapps supported | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Xstack projects involved | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Internal representation used | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Key Optimizations performed | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Code generation technology used | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Processors/computing models targeted | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Current status | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) | ||
| Summary of the best results | (EXPRESS) | (TG) | (DEGAS) | (D-TEC) | (DynAX) | (X-TUNE) | (GVR) | (CORVETTE) | N/A | (PIPER) |