March 20 2013 Panel Sessions: Difference between revisions
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Exascale systems will impose a fresh set of requirements on runtime systems that include targeting nodes with hundreds of homogeneous and heterogeneous cores, as well as energy, data movement and resiliency constraints within and across nodes. This session will focus on the fundamental research challenges that need to be addressed in the area of runtimes for exascale systems. Both panelists and audience members are expected to play an active role in the discussion. | Exascale systems will impose a fresh set of requirements on runtime systems that include targeting nodes with hundreds of homogeneous and heterogeneous cores, as well as energy, data movement and resiliency constraints within and across nodes. This session will focus on the fundamental research challenges that need to be addressed in the area of runtimes for exascale systems. Both panelists and audience members are expected to play an active role in the discussion. | ||
[[media:Runtime-Panel-v5.pdf|Runtime Systems]] | |||
[[Runtime_Research_Questions| Questions and Discussion]] | [[Runtime_Research_Questions| Questions and Discussion]] | ||
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The panelists in this parallel session will engage the audience in discussing the advances in compiler technology that are available and needed for the X-Stack program to support exascale computing systems. To save power, exascale systems will present many new features far beyond what we face today in terms of heterogeneity, explicit memory and communications management, load balancing and throttling, imbalance, demand for concurrency, deep (e.g. 10 level) memory hierarchies, new messaging and collectives, fault tolerance and new execution models (e.g., codelets). Furthermore, at these scales, the algorithms employed by systems will change radically and existing code bases will obselete accordingly. There will be a greater emphasis on irregularity, locality and placement, asynchronity, relaxed precision, communication avoidance, combinatorics, new solvers, and in-situ analysis and uncertainty quantification. The panelists will discuss how their teams' research in the X-Stack program bridges between new exascale algorithms and new exascale hardware. | The panelists in this parallel session will engage the audience in discussing the advances in compiler technology that are available and needed for the X-Stack program to support exascale computing systems. To save power, exascale systems will present many new features far beyond what we face today in terms of heterogeneity, explicit memory and communications management, load balancing and throttling, imbalance, demand for concurrency, deep (e.g. 10 level) memory hierarchies, new messaging and collectives, fault tolerance and new execution models (e.g., codelets). Furthermore, at these scales, the algorithms employed by systems will change radically and existing code bases will obselete accordingly. There will be a greater emphasis on irregularity, locality and placement, asynchronity, relaxed precision, communication avoidance, combinatorics, new solvers, and in-situ analysis and uncertainty quantification. The panelists will discuss how their teams' research in the X-Stack program bridges between new exascale algorithms and new exascale hardware. | ||
[[media:CompilerPanel_Summary.pptx|Compiler Panel Summary]] | |||
[[Compilers_Research_Questions| Questions and Discussion]] | [[Compilers_Research_Questions| Questions and Discussion]] | ||
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Speakers (to be confirmed): John Mellor-Crummey, Andrew Lumsdaine, Armando Solar-Lezama, Emina Torlak, John Feo | Speakers (to be confirmed): John Mellor-Crummey, Andrew Lumsdaine, Armando Solar-Lezama, Emina Torlak, John Feo | ||
This session will cover the concepts used in various general purpose and domain specific programming languages (DSLs). Members of the audience will also be encouraged to participate to provide additional perspective on how specific features of the languages involved in the X-Stack projects and elsewhere are meeting various challenges. (The following questions are written assuming that a speaker is presenting a particular language, but can also be answered more generally for what an Exascale language should have. And “language” is used to refer to both general purpose and domain-specific languages.) | This session will cover the concepts used in various general purpose and domain specific programming languages (DSLs). Members of the audience will also be encouraged to participate to provide additional perspective on how specific features of the languages involved in the X-Stack projects and elsewhere are meeting various challenges. (The following questions are written assuming that a speaker is presenting a particular language, but can also be answered more generally for what an Exascale language should have. And “language” is used to refer to both general purpose and domain-specific languages.) | ||
[[media:GPLs-DSLs-Summary-2013.pptx|General Purpose and Domain Specific Languages (GPLs and DSLs)]] | |||
[[Languages_Research_Questions| Questions and Discussion]] | [[Languages_Research_Questions| Questions and Discussion]] | ||
Latest revision as of 03:40, December 25, 2013
Runtime Research
Moderator: Vivek Sarkar Panelists: Greg Bronevetsky (LLNL), Zoran Budimlic (Rice), Paul Hargrove (LBNL) Hartmut Kaiser (LSU), Sriram Krishnamoorthy (PNNL), Olivier Tardieu (IBM), Rishi Khan (ETI)
Exascale systems will impose a fresh set of requirements on runtime systems that include targeting nodes with hundreds of homogeneous and heterogeneous cores, as well as energy, data movement and resiliency constraints within and across nodes. This session will focus on the fundamental research challenges that need to be addressed in the area of runtimes for exascale systems. Both panelists and audience members are expected to play an active role in the discussion.
Compilers Research
Moderator: Dan Quinlan Panelists (to be confirmed): Milind Kulkarni (Purdue), David Padua (UIUC), P. Sadayappan (Ohio State), Armando Solar-Lezama (MIT), Olivier Tardieu (IBM), Nicolas Vasilache (Reservoir)
The panelists in this parallel session will engage the audience in discussing the advances in compiler technology that are available and needed for the X-Stack program to support exascale computing systems. To save power, exascale systems will present many new features far beyond what we face today in terms of heterogeneity, explicit memory and communications management, load balancing and throttling, imbalance, demand for concurrency, deep (e.g. 10 level) memory hierarchies, new messaging and collectives, fault tolerance and new execution models (e.g., codelets). Furthermore, at these scales, the algorithms employed by systems will change radically and existing code bases will obselete accordingly. There will be a greater emphasis on irregularity, locality and placement, asynchronity, relaxed precision, communication avoidance, combinatorics, new solvers, and in-situ analysis and uncertainty quantification. The panelists will discuss how their teams' research in the X-Stack program bridges between new exascale algorithms and new exascale hardware.
Languages and DSLs
Moderator: Kathy Yelick Speakers (to be confirmed): John Mellor-Crummey, Andrew Lumsdaine, Armando Solar-Lezama, Emina Torlak, John Feo
This session will cover the concepts used in various general purpose and domain specific programming languages (DSLs). Members of the audience will also be encouraged to participate to provide additional perspective on how specific features of the languages involved in the X-Stack projects and elsewhere are meeting various challenges. (The following questions are written assuming that a speaker is presenting a particular language, but can also be answered more generally for what an Exascale language should have. And “language” is used to refer to both general purpose and domain-specific languages.)
General Purpose and Domain Specific Languages (GPLs and DSLs)
Auto tuning and Learning
Moderator: Saman Amarasinghe (MIT) Panelist: Cy Chan (LBNL), Sam WIlliams (LBNL), Mary Hall (Utah), Una-May O’Reily (MIT)
Because of the extreme complexity of the high performance software and hardware, it is becoming impossible to model and understand the behavior of end-to-end system and manually optimize them for performance. One important solution optimizing complex high performance systems is autotuning. Autotuning uses machine learning techniques to explore the optimization space with empirical evaluation of the performance. In this panel we will discuss:
Resilience
Moderator: Andrew A. Chien (University of Chicago/ANL) Panelists: Greg Bronevetsky (LLNL), Bob Lucas (USC/ISI), Sriram Krishnamoorthy (PNNL), Josep Torrellas (Illinois), Saman Amarasinghe (MIT)
The panelists in this parallel session will engage the audience in discussing various resilience technologies – extant and emerging – and their capabilities to address different types of resilience challenges. Panelists will also discuss how each of these technologies will be demonstrated a promising, how they might be incorporated in future x-stacks (cross program synergy), or presented for direct use by applications program experiments.
Simulation technology
Moderator: Shekhar Borkar Panelists: Arun Rodrigues, John Shalf, Rishi Khan, Krste Asanovic, Greg Bronevetsky
The panelists in this parallel session will engage the audience in discussing various simulation technologies to evaluate and mature software components of the X-Stack program. This evaluation using simulators will also provide guidance for the hardware design. Behavioral simulators are fast, capable of running software close to real time; on the other hand, functional simulators are slower but model the hardware more accurately. Time accurate simulators are even slower, but provide precise timing information much needed to evaluate certain hardware-software interactions. Emulation technology provides time accuracy as well as speed for software evaluation, but is resource and time intensive. Each of these technologies have their pluses and minus, and the panel will discuss their role in the X-Stack program to evaluate software components with hardware interaction, using metrics such as performance, energy, and implementation.