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Traleika Glacier

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Revision as of 21:30, August 8, 2014 by imported>WilliamFeiereisen (→‎Meetings and Workshops)
Traleika Glacier X-Stack
Traleikaglacier.jpg
Team Members Intel, Reservoir Labs, ETI, UDEL, UC San Diego, Rice U., UIUC, PNNL
PI Shekhar Borkar (Intel)
Co-PIs Wilf Pinfold (Intel), Richard Lethin (Reservoir Labs), TBD (ETI), Guang Gao (UDEL), Laura Carrington (UC San Diego), Vivek Sarkar (Rice U.), David Padua (UIUC), Josep Torrellas (UIUC), John Feo (PNNL)
Website https://www.xstackwiki.com/index.php/Traleika_Glacier
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Team Members


Goals and Objectives

Goal: The Traleika Glacier X-Stack program will develop X-Stack software components in close collaboration with application specialists at the DOE co-design centers and with the best available knowledge of the Exascale systems we anticipate will be available in 2018/2020.

Description: Intel has built a straw-man hardware platform that embodies potential technology solutions to well understood challenges. This straw-man is implemented in the form of a simulator that will be used as a tool to test software components under investigation by Traleika team members. Co-design will be achieved by developing representative application components that stress software components and platform technologies and then use these stress tests to refine platform and software elements iteratively to an optimum solution. All software and simulator components will be developed in open source facilitating open cross team collaboration. The interface between the software components and the simulator will be built to facilitate back end replacement with current production architectures (MIC and Xeon) providing a broadly available software development vehicle and facilitating the integration of new tools and compilers conceived and developed under this proposal with existing environments like MPI, OpenMP, and OpenCL.

The Traleika Glacier X-Stack team brings together strong technical expertise from across the exascale software stack. Utilizing applications of high interest to the DoE from five National Labs, coupled with software systems expertise from Reservoir Labs, ET International, the University of Illinois, University of California San Diego, University of Delaware, and Rice University, using a foundation of platform excellence from Intel. This project builds collaboration between many of the partners making this team uniquely capable of rapid progress. The research is not only expected to further the art in system software for high performance computing but also provide invaluable feedback thru the co-design loop for hardware design and application development. By breaking down research and development barriers between layers in the solution stack this collaboration and the open tools it produces will spur innovation for the next generation of high performance computing systems.


Objectives:

  • Energy efficiency: SW components interoperate, harmonize, exploit HW features, and optimize the system for energy efficiency
  • Data locality: PGM system & system SW optimize to reduce data movement
  • Scalability: SW components scalable, portable to O(109)—extreme parallelism
  • Programmability: New (Codelet) & legacy (MPI), with gentle slope for productivity
  • Execution model: Objective function based, dynamic, global system optimization
  • Self-awareness: Dynamically respond to changing conditions and demands
  • Resiliency: Asymptotically provide reliability of N-modular redundancy using HW/SW co-design; HW detection, SW correction

Status Reports

Meetings and Workshops

  • Applications Workshop #3 - To be held September 30, 2014 - October 2, 2014 @ Intel in Hillsboro, OR
  • Agenda:

Publications

Intel

  • Programmer Obliviousness is Bliss: Ideas for Runtime-Managed Granularity, Romain Cledat, Sagnak Tasirlar (Rice University) and Rob Knauerhase (Intel). To be published at HotPar ’13, June 24, 2013, San Jose, CA - https://www.usenix.org/conference/hotpar13
  • How to stop interconnects from hindering the future of computing!, Shekhar Borkar, Optical interconnects Conference, May 2013
  • Exascale Computing—a fact or a fiction?, Shekhar Borkar, IPDPS, May 2013
  • Functional Simulator for Exascale System Research, Romain Cledat (Intel), Josh Fryman (Intel), Ivan Ganev (Intel), Sam Kaplan (ETI), Rishi Khan (ETI), Asit Mishra (Intel), Bala Seshasayee (Intel), Ganesh Venkatesh (Intel), Dave Dunning (Intel), Shekhar Borkar (Intel), Workshop on Modeling & Simulation of Exascale Systems & Applications, September 18th-19th, 2013, University of Washington, Seattle, WA - http://hpc.pnl.gov/modsim/2013/

Reservoir Labs

  • A Tale of Three Runtimes, Nicolas Vasilache, Muthu Baskaran, Tom Henretty, Benoit Meister, M. Harper Langston, and Richard Lethin, to appear in arXiv.org

Rice University

  • Integrating Asynchronous Task Parallelism with MPI. Sanjay Chatterjee, Sağnak Taşırlar, Zoran Budimlić, Vincent Cavé, Millind Chabbi, Max Grossman, Yonghong Yan and Vivek Sarkar. 27th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2013), May 2013, Boston, MA.
  • Compiler Optimization of an Application-specific Runtime, Kathleen Knobe (Intel) and Zoran Budimlić (Rice), CPC 2013: 17th Workshop on Compilers for Parallel Computing, July 3-5, 2013, Lyon, France. (to appear).
  • Compiler Optimization of an Application-specific Runtime. Kathleen Knobe (Intel) and Zoran Budimlic (Rice). In Compilers for Parallel Computers (CPC), July 2013.
  • Compiler Optimization of an Application-specific Runtime. Kathleen Knobe (Intel) and Zoran Budimlic (Rice). Abstract to appear in CnC'13 workshop, September 2013.
  • Automatic Selection of Distribution Functions for Distributed CnC, Kamal Sharma (Rice), Kathleen Knobe (Intel), Frank Schlimbach (Intel), Vivek Sarkar (Rice). Abstract to appear in CnC'13 workshop, September 2013.
  • CnC on Open Community Runtime, Alina Sbirlea (Rice) and Zoran Budimlic (Rice). Abstract to appear in CnC'13 workshop, September 2013.
  • Bounded Memory Scheduling of CnC Programs, Dragos Sbirlea (Rice), Zoran Budimlic (Rice) and Vivek Sarkar (Rice). Abstract to appear in CnC'13 workshop, September 2013.
  • CDSC-GL: A CnC-inspired Graph Language, Zoran Budimlic (Rice), Jason Cong (UCLA), Zhou Li (UCLA), Louis-Noel Pouchet (UCLA), Vivek Sarkar (Rice), Alina Sbirlea (Rice), Mo Xu (UCLA), Pen Zhang (UCLA). Abstract to appear in CnC'13 workshop, September 2013.
  • Bounded memory scheduling of dynamic task graphs, Dragos Sbirlea, Zoran Budimlić, Vivek Sarkar, submitted to IPDPS 2014.
  • Isolation for Nested Task Parallelism, Jisheng Zhao, Roberto Lublinerman, Zoran Budimlic, Swarat Chaudhuri, Vivek Sarkar, The 29th International Conference on the Object-Oriented Programming, System, Languages and Application (OOPSLA), October 2013.
  • Bounded memory scheduling of dynamic task graphs, Dragos Sbirlea, Zoran Budimlic, Vivek Sarkar, to appear in The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014).
  • Expressing DOACROSS Loop Dependencies in OpenMP, Jun Shirako, Priya Unnikrishnan, Sanjay Chatterjee, Kelvin Li, Vivek Sarkar, 9th International Workshop on OpenMP (IWOMP), September 2013.
  • The Flexible Preconditions Model for Macro-Dataflow Execution, Dragoș Sbîrlea, Alina Sbîrlea, Kyle B. Wheeler, Vivek Sarkar, The 3rd Data-Flow Execution Models for Extreme Scale Computing (DFM), September 2013.

Pacific Northwest National Lab

  • ACDT: Architected Composite Data Types Trading-in Unfettered Data Access for Improved Execution, Marquez, A. et.al, submitted to the 23rd International ACM symposium on High Performance Parallel and Distributed Computing 2014, Vancouver Canada.

University of Delaware

  • An Implementation of the Codelet Model, Joshua Suetterlein, Stephane Zuckerman, and Guang R. Gao, to be published in the proceedings of the 19th International European Conference on Parallel and Distributed Computing (EuroPar 2013), August 26-30, Aachen, Germany.
  • Towards Memory-Load Balanced Fast Fourier Transformations in Fine-Gain Execution Models, Chen Chen, Yao Wu, Stephane Zuckerman, and Guang R. Gao, to be published in Proceedings of 2013 Workshop on Multithreaded Architectures and Applications (MTAAP 2013). 27th IEEE International Parallel & Distributed Processing Symposium, May 24, Boston, MA, USA.
  • Toward a Self-Aware System for Exascale Architectures[1], Aaron Myles Landwehr, Stephane Zuckerman, Guang R. Gao, CAPSL Technical Memo 123, June 2013.
  • Optimizing the LU Factorization for Energy Efficiency on a Many-Core Architecture, Elkin Garcia, Jaime Arteaga, Robert Pavel, and Guang R. Gao, in Proceedings of the 26th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2013), Santa Clara, CA, September 25-27, 2013.
  • Position Paper: Locality-Driven Scheduling of Tasks for Data-Dependent Multithreading, Jaime Arteaga, Stephane Zuckerman, Elkin Garcia, and Guang R. Gao, in Proceedings of Workshop on Multi-Threaded Architectures and Applications (MTAAP 2014), May 2014, Accepted.
  • Runtime Systems for Extreme Scale Platforms, Sanjay Chatterjee, PhD Thesis, December 2013.

Joint Publications

  • Compiler Support for Software Cache Coherence, Sanket Tavarageri, Wooil Kim, Josep Torrellas, and P Sadayappan Pacific Northwest National Labs (John Feo, Andres Marquez), submitted for publication.
  • A Dynamic Schema to increase performance in Many-core Architectures through Percolation operations, Elkin Garcia, Daniel Orozco, Rishi Khan, Ioannis Venetis, Kelly Livingston, and Guang Gao, in Proceedings of the 2013 IEEE International Conference on High Performance Computing (HiPC 2013), Hyderabad, India, December 18 - 21, 2013.
  • ASAFESSS: A Scheduler-driven Adaptive Framework for Extreme Scale Software Stacks, Tom St. John, Benoit Meister, Andres Marquez, Joseph B. Manzano, Guang R. Gao, and Xiaoming Li, in Proceedings of the 4th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT'14); 9th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC'14), Vienna, Austria. January 20-22, 2014. Best Paper Award.

Presentations and Other Collateral

CnC’13 workshop September, 2013

The following were presented at the CnC’13 workshop September, 2013. This was the fifth annual CnC workshop. It was co-located with Languages and Compilers for Parallel Systems (LCPC) in Santa Clara, CA.

  • Compiler Optimization of an Application-Specific Runtime. Kathleen Knobe (Intel) and Zoran Budimlic (Rice). *
  • The CnC tuning capability, Sanjay Chatterjee (Rice), Zoran Budimlic (Rice), Vivek Sarkar (Rice), Kathleen Knobe (Intel).
  • Automatic Selection of Distribution Functions for Distributed CnC, Kamal Sharma (Rice), Kathleen Knobe (Intel), Frank Schlimbach (Intel), Vivek Sarkar (Rice)*.
  • CnC on Open Community Runtime, Alina Sbirlea (Rice) and Zoran Budimlic (Rice).
  • Bounded Memory Scheduling of CnC Programs, Dragos Sbirlea (Rice), Zoran Budimlic (Rice) and Vivek Sarkar (Rice). *
  • CDSC-GL: A CnC-inspired Graph Language, Zoran Budimlic (Rice), Jason Cong (UCLA), Zhou Li (UCLA), Louis-Noel Pouchet (UCLA), Vivek Sarkar (Rice), Alina Sbirlea (Rice), Mo Xu (UCLA), Pen Zhang (UCLA).*
  • Implementing Asynchronous Checkpoint/Restart for CnC, Nick Vrvilo and Vivek Sarkar (Rice University) Kath Knobe and Frank Schlimbach(Intel)
  • Automatic CnC generation from a sequential specification, Nicolas Vasilache (Reservoir Labs, Inc.)

Note: Asterisked (*) presentations are supportive of the Traleika Glacier X-Stack strategic aims and objectives but not directly under the statement of work.

About OCR - Open Community Runtime

Scope of the Project

TG-Scope.png


Roadmap

TG-Roadmap.png


Architecture

Straw-man System Architecture and Evaluation

TG-Strawman-System.png


Data-locality and BW Tapering, Why So Important?

TG-Data-Locality.png


Programming and Execution Models

TG-Programming-Model.png

Programming model

  • Separation of concerns: Domain specification & HW mapping
  • Express data locality with hierarchical tiling
  • Global, shared, non-coherent address space
  • Optimization and auto generation of codelets (HW specific)

Execution model

  • Dataflow inspired, tiny codelets (self contained)
  • Dynamic, event-driven scheduling, non-blocking
  • Dynamic decision to move computation to data
  • Observation based adaption (self-awareness)
  • Implemented in the runtime environment

Separation of concerns

  • User application, control, and resource management


Programming System Components

TG-System-Components.png

Runtime

  • Different runtimes target different aspects
    • IRR: targeted for Intel Straw-man architecture
    • SWARM: runtime for a wide range of parallel machines
    • DAR3TS: explore codelet PXM using portable C++
    • Habanero-C: interfaces IRR, tie-in to CnC
  • All explore related aspects of the codelet Program Exec Model (PXM)
  • Goal: Converge towards Open Collaborative Runtime (OCR)
    • Enabling technology development for codelet execution
    • Model systems, foster novel runtime systems research
  • Greater visibility through SW stack -> efficient computing
    • Break OS/Runtime information firewall


Some Promising Results:

TG-Runtime-Results.png

Runtime Research Agenda

  • Locality aware scheduling—heuristics for locality/E-efficiency
    • Extensions to standard Habanero-C runtime
  • Adaptive boosting and idling of hardware
    • Avoid energy expensive unsuccessful steals that perform no work
    • Turbo mode for a core executing serial code
    • Fine grain resource (including energy) management
  • Dynamic data-block movement
    • Co-locate codelets and data
    • Move codelets to data
  • Introspection and dynamic optimization
    • Performance counters, sensors provide real time information
    • Optimization of the system for user defined objective
    • (Go beyond energy proportional computing)


Simulators and Tools

TG-Simulators-Tools.png


Simulators—what to expect and not

  • Evaluation of architecture features for PGM and EXE models
  • Relative comparison of performance, energy
  • Data movement patterns to memory and interconnect
  • Relative evaluation of resource management techniques

TG-Simulator-Expect-Not.png


Results Using Simulators

TG-Simulator-Results.png


Applications and HW-SW Codesign

TG-App-HW-Co-design.png


X-Stack Components

TG-XStack-Components.png


Metrics

TG-Metrics.png

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